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    "name": "CTS error with split voltage IO cells",
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      "content": "When trying to use the ocd version of the IO cells, I see this error in CTS:\n```\n[INFO CTS-0007] Net \"clk_PAD2CORE\" found for clock \"clk_PAD\".\n[INFO CTS-0122] Clock net \"clk_PAD2CORE\" is skipped for CTS because it is not connected to any output instance pin or input block terminal.\n[WARNING CTS-0083] No clock nets have been found.\n[INFO CTS-0008] TritonCTS found 0 clock nets.\n[WARNING CTS-0082] No valid clock nets in the design.\n```\nI've confirmed it happens on the default template too.  There it doesn't cause the build to fail - presumably the tooling can cope without needing a clock tree for a small number of registers, but it's obviously bad, and in a larger design it does cause failures.",
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      "content": "Can confirm, that is not a nice clock tree. (I'm also wondering why I don't see the SPEF delays here.)",
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      "content": "I'll compare the LEF/LIB views of the OCD cells with the foundry ones.",
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      "content": "Found the issue: `PIN Y` in the LEF does not have a direction set, making it `INPUT` by default.\n\nYou can edit `libs.ref/gf180mcu_ocd_io/lef/gf180mcu_ocd_io.lef` and add `DIRECTION OUTPUT ;` after line 3432.",
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      "content": "Thanks for the report, Mike! I'll make sure the PDK is updated accordingly.",
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